1. Field of the Invention
This invention generally relates to data processing systems and more specifically to apparatus for diagnosing errors in such a system.
2. Discussion of the Prior Art
It is well known that data processing systems provide checking apparatus for conditioning the system to be manually stepped through its operation either in a software instruction by software instruction basis or on a cycle by cycle basis. Additionally, some systems provide for halting system operation on a particular instruction which bears address designated by selector switches on a control panel. An example of such an arrangement is disclosed in U.S. Pat. No. 3,077,984. Additionally, some systems provide for halting system operation on a particular instruction operation code specified by setting up a plurality of switches which are used to specify the bit pattern of the operation code. An example of such an arrangement is disclosed in U.S. Pat. No. 3,813,531 issued to Richard L. King et al, and entitled "Diagnostic Checking Apparatus". More recently, with the advent of microprogrammed control stores, systems have been designed to provide for the halting of the control store at a specified control store address or microinstruction bit pattern. An example of such an arrangement is disclosed in U.S. Pat. No. 3,909,802 issued to Frank V. Cassarino, Jr., et al, entitled "Diagnostic Maintenance and Test Apparatus".
While the arrangements described above assist maintenance personnel in diagnosing system malfunctions, these arrangements cannot be used in systems employing semiconductor random access memories which are periodically recharged under microprogram control. For example, if a microprogram periodically issues memory refresh commands to the rechargeable memory, halting the execution of the microprogram will rapidly result in the loss of the information contained within the rechargeable memory. Alternatively, in a system designed such that the rechargeable memory is refreshed asynchronously from the microprogram executing in the control store, logic must be provided within the system to recover from those cases in which the unit desiring to access the rechargeable memory finds the memory temporarily busy because the memory is engaged in a refresh operation.